1. Field of the Invention
The present invention relates to a method of generating a test clock signal and a test clock signal generator. More particularly, the present invention relates to a method of generating a test clock signal and a test clock signal generator for testing semiconductor devices.
2. Description of the Related Art
A wafer passed through a fabrication process includes multiple chips having substantially the same structure, referred to as “die.” Generally, some chips on the wafer may have defects. Thus, a sorting process, which determines whether chips are defective and isolates the defective chips, is important. Sorting processes may be performed on the chips on a wafer or may be performed on packaged semiconductor devices.
A pad is an input/output part in a semiconductor device. The semiconductor device may receive an electric signal from an external source or send an electric signal to an external receiver through the pad.
During a testing process, variables such as signal delay, current capacity, etc., are checked, referred to as a “parameter test.” In addition, semiconductor devices are checked to determine whether the semiconductor devices properly perform a designed operation, referred to as a “function test.” Generally, semiconductor devices including a logic circuit also undergo a scan test, and semiconductor devices including a memory device also undergo a built-in self test (BIST).
FIG. 1 is a block diagram illustrating a conventional test system for semiconductor devices. Referring to FIG. 1, a test system 100 includes a tester 110 and a semiconductor device 120.
The tester 110 rapidly provides the semiconductor device 120 with variable test signals for operating the semiconductor device 120 under actual conditions. When the semiconductor device 120 receives the test signals, it operates according to the test signals and the tester 110 determines whether the semiconductor device 120 performs a predetermined operation. When the semiconductor device 120 does not perform the predetermined operation, the tester 110 treats the semiconductor device 120 as a defective semiconductor device.
Recently, operating frequencies of internal logic circuits in semiconductor devices have gradually increased. The operating frequency of an internal logic circuit in some semiconductor devices is over 400 MHz. In contrast, the maximum clock frequency presently used is generally no more than about 200 MHz. A tester that has a high clock frequency and is accurate is very expensive. Use of an expensive tester increases the cost of manufacturing the semiconductor devices.
In addition, the pads which provide the input/output passages of the semiconductor devices may not transmit high frequency signals. As a result, although a tester capable of providing high frequency test signals may exist, the internal logic circuit in the semiconductor devices may not actually receive the high frequency test signals. Thus, the semiconductor devices must have pads with a good frequency response. However, pads having a good frequency response further increase production costs of the semiconductor devices.
FIG. 2 is a timing diagram illustrating a conventional scan test. Generally, the scan test has two shift periods 210 and 230 and a capture period 220.
During the shift periods 210 and 230, test vectors are input, and during the capture period 220, a logic circuit between flip-flops in a semiconductor device is tested, based on the test vectors. A test for the internal logic circuit in the semiconductor device by a real operating frequency is referred to as an “at-speed test,” which is performed in the capture period 220. As illustrated in FIG. 2, the capture period 220 includes a gated clock signal that is generated by gating a clock signal generated by a phase-locked loop (PLL) in the semiconductor device. The flip-flops in the semiconductor device operate synchronized with the gated clock signal.
In relation to the at-speed test, U.S. Patent Application Publication Number 2003/0009714 to EVANS discloses a test system for testing a semiconductor device having a high speed operating frequency by using a tester having a low speed clock frequency. EVANS discloses a scan test process having shift periods and a capture period, and discloses that a number of pulses included in a gated clock signal in the capture period may be selected.
For testing according to the conventional test systems, a clock signal generator that efficiently generates a clock signal used in the shift periods and the capture period is required.